SYNC_BYPASS=SYNCHRONIZE, POLARITY=RISING, DBLBUF_ENA=DISABLED, SHUTOFF_ENA=DISABLED, TRIG_SRC=INTERNAL, TIMER_ENA=DISABLED
DAC Control register. This register contains bits to configure DAC operation and the interrupt/dma request flag.
| INT_DMA_FLAG | Interrupt/DMA request flag. This bit is read-only. 0 = This bit is cleared upon any write to the DACVAL register. 1 = This bit is set by hardware only if a hardware trigger has been selected as follows: - If the internal timer is selected, this bit will be set when the timer times-out. - If an external trigger input is selected, this bit will be set when a transition of the specified polarity is detected on the selected input. |
| TRIG_SRC | Hardware Trigger Source: If anyof these hardware trigger sources are selected, an interrupt/dma request will be generated when the specified trigger occurs. In addition, if double-buffering is enabled (the DBLBUF_ENA’ bit is set), the DACVAL register will be loaded from the pre-buffer at the same time. 0 (INTERNAL): Internal. Selects the internal timer as the trigger source provided the timer is enabled (the TIMER_ENA bit is set). Otherwise (if the timer is not enabled), hardware triggering is disabled. If hardware triggering is disabled no interrupt or DMA requests will be generated. Double-buffering of the DAC VAL register is not useful and cannot be enabled when hardware triggering is disabled. 1 (PIN): Pin. External DAC_TRIG port input is selected. Also select this function in the PINASSIGN11 register in the switchmatrix. |
| POLARITY | Specifies the polarity of the selected external trigger input. Does not apply if the TRIG_SRC field is set to 0. 0 (RISING): Rising. A trigger will be asserted when a RISING edge is detected on the selected external trigger input. 1 (FALLING): Falling. A trigger will be asserted when a FALLING edge is detected on the selected external trigger input. |
| SYNC_BYPASS | Permits bypassing of one synchronization flip-flop, if not required. Does not apply if the TRIG_SRC field is set to 0. 0 (SYNCHRONIZE): Synchronize. The selected trigger input will be synchronized to the system clock prior to edge-detection. 1 (NOT_SYNCHRONIZE): Not synchronize. The selected trigger input will not be synchronized to the system clock prior to edge-detection. This will save one clock of latency. This bit should only be set f the selected hardware input trigger is from a source that is guaranteeed to already be synchronous to the system clock. |
| TIMER_ENA | Timer Enable 0 (DISABLED): Disabled. The internal timer is disabled. If the TRIG_SEL field is also set to 000 then hardware triggering is disabled. 1 (ENABLED): Enabled. The internal timer is enabled and counting. Note: This bit should only be set after a valid count value has been programmed into the DACCNTVAL register. |
| DBLBUF_ENA | Double-Buffer Enable. 0 (DISABLED): Disabled. Double-buffering of the DACVAL register is disabled. Software writes to the DACVAL address will directly modify the DAC data presented to the D/A converter. Hardware trigger events, if selected, will not affect the DACVAL contents. 1 (ENABLED): Enabled. The double-buffering feature in the DACVAL register is enabled. Writes to the DACVAL register are written to a pre-buffer and then transferred to the DACVAL when the specified hardware trigger occurs. Setting this bit will have no effect if hardware triggering is disabled. Double-buffering is of no value under this condition. |
| SHUTOFF_ENA | Shutoff Enable 0 (DISABLED): Disabled. The hardware DAC-shutoff feature is disabled. 1 (ENABLED): Enabled. The hardware DAC-shutoff feature is enabled. Whenever the DAC_SHUTOFF (port pin) input is high, the DAC output voltage will be forced to zero. The DAC output will return to the value specifed in the DACVAL register once the input pin returns to the low state. |
| SHUTOFF_FLAG | Shutoff Flag. This is a read-only bit. Reflects the state of the DAC_SHUTOFF input if the Shutoff feature is enabled. 0 = DAC_SHUTOFF (port pin) input is low. DAC is outputting the voltage specified in the DAC VAL register. 1 = DAC_SHUTOFF (port pin) input is high. The DAC output is forced to zero. This bit serves as a flag only, If a processor interrupt is desired when a DAC shutoff condition occurrs, that can be accomplished by enabling the port pin selected as the DAC_SHUTOFF pin to directly generate a port interrupt. |
| BIAS | These bits permit trading-off longer DAC settling times to achieve reduced power consumption. The default setting provides maximum speed but also maximum power. |
| RESERVED | Reserved. Software should only write zeros to unused bits. |